Highly energy and performance efficient embedded computing through approximately correct arithmetic: A mathematical foundation and preliminary experimental validation

We develop a theoretical foundation to characterize a novel methodology for low energy and high performance dsp for embedded computing. Computing elements are operated at a frequency higher than that permitted by a conventionally correct circuit design, enabling a trade-off between error that is deliberately introduced, and the energy consumed. Simi-lar techniques considered previously were relevant to deeply scaled future technology generations. Our work extends this idea to be applicable to current-day designs through: (i) a mathematically rigorous foundation characterizing a trade-off between energy consumed and the quality of solution, and (ii) a means of achieving this trade off through very aggres-sive voltage scaling beyond that of a conventionally designed circuit. Through our “cmos inspired ” mathematical model, we show that our approach is better (by an exponential fac-tor) than the conventional uniform voltage scaling approach for comparable computational speed or performance. We fur-ther establish through experimental study that a similar im-provement by a factor of 3.4x to the snr over conventional voltage-scaled approaches can be achieved in the context of the ubiquitous discrete Fourier transform. ∗This author wishes to thank the the Moore distinguishe