A Digitally Programmable Delay Element: Design and Analysis

Abstract—Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in inte-grated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay el-ements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteris-tics over previously reported digitally controlled delay elements. Index Terms—Analysis, delay, design, digital CMOS, locked-loop, test