Abstract DREM: ARCHITECTURAL SUPPORT FOR DETERMINISTIC REDUNDANT EXECUTION OF MULTITHREADED PROGRAMS

Recently there have been several proposals to use redundant execution of diverse repli-cas to defend against attempts to exploit memory corruption vulnerabilities. However, redundant execution relies on the premise that the replicas behave deterministically, so that if inputs are replicated to both replicas, any divergences in their outputs can only be the result of an attack. Unfortunately, this assumption does not hold for multithreaded programs, which are becoming increasingly prevalent – the non-deterministic interleaving of threads can also cause divergences in the replicas. This thesis presents a method to eliminate concurrency related non-determinism be-tween replicas. We introduce changes to the existing cache coherence hardware used in multicores to support deterministic redundant execution. We demonstrate that our solution requires moderate hardware changes and shows modest overhead in scientific applications. ii Acknowledgements First, I would like to thank Professor David Lie for his countless contributions, guidance, and support for this project. His encouragement and expertise helped formulate many of the ideas found in this work