Accelerating Test Generation by VLSI Hardware Emulation

A hardware emulation system based on a programmable VLSI array is used for test pattern generation for combinational circuits. The real-time simulation capability of the hardware emulator significantly improves time required for test generation time. The VLSI hardware emulator implements a parallel algorithm for test pattern generation based on neural networks. Test generation is achieved by mapping a circuit into its equivalent VLSI array test generation model emulating this test generation algorithm. The programmed array serves as a hardware accelerator for automatic test pattern generation Impact: The main impact of this method is in test generation of combinational circuits. Combining our VLSI programmable cells with shift register cells for register modeling and scan insertion, a complete digital system can be modeled for test generation in a VLSI emulator. Another potential application of this work is in digital implementation of a limited form of Hopfield neural networks