Delft-Java Dynamic Translation

This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM in-structions into DELFT-JAVA instructions. Using a form of hardware register allocation, we transform stack bottle-necks into pipeline dependencies which are later removed using register renaming and interlock collapsing arithmetic units. When combined with superscalar techniques and multiple instruction issue, we remove up to 60 % of trans-lated dependencies. When compared with a realizable stack-based implementation, our approach accelerates a Vector Multiply execution by 3.2x for out-of-order execu-tion with register reanaming and 2.7x when hardware con-straints were considered. In addition, for translated instruc-tion streams, we realized a 50 % performance improvement for out-of-order execution when compared with in-order ex-ecution.