A method of redundant clocking detection and power reduction at RT level design

This paper proposes a novel method to estimate and to re-duce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redun-dant clockings which activate registers unnecessarily, we de-tect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a regis-ter. And then we introduce gated-clock scheme to reduce the power consumption of the circuits using our estimation re-sults. Experimental results demonstrate the accuracy of our method and the effect on power reduction.