Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores

As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a “hard ” layout. In this paper, we focus on an alternative approach: vendors supply a synthesizable version of their programmable logic core (a “soft ” core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating “hard ” cores into an ASIC. For very small amounts of logic, this ease of use may be more important than the increased overhead. This paper presents two synthesizable programmable logic core architectures, describes the associated place and route CAD tools, and compares the two architectures to each other, and to a “hard ” programmable logic core. It also shows how these cores can be made more efficient by creating a non-rectangular architecture, an option not available to “hard ” core vendors