Hardware-Compiler Co-Design for Adjustable Data Power Savings

To accomodate standards changes and algorithmic im-provements, functional reconfigurability is increasingly de-sired for media processing. Such adaptability, however, gen-erally comes at significant power cost. This work suggests that another dimension of adaptation can be beneficial – power adaptation. Through a unique compiler–hardware ap-proach, we (1) demonstrate an extension to the state-of-the-art in data analyzability, yielding better control over scratch-pad data management, and (2) combine this knowledge with an SRAM having variable latency and access properties, yielding adjustable power savings. Building upon the com-piler techniques presented in [1], we evaluate the severity of the current on-chip storage power problem and detail how SRAM structures can be built to enable data power sav-ings for media applications. We show how the implemented compiler techniques can be applied to other problems in the embedded/media processing domain, and present net data power savings results for a suite of media and telecommu