AUTOMATIC SYNTHESIS OF TTA PROCESSOR NETWORKS FROM RVC-CAL DATAFLOW PROGRAMS

The RVC-CAL dataflow language has recently become stan-dardized through its use as the official language of Recon-figurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transfor-mation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruc-tion processors and HDL synthesis. This paper introduces new tools that enable synthesizing RVC-CAL dataflow programs automatically into application specific processor networks. Each processor in the network performs the functionality of one RVC-CAL actor. The pro-cessors are of the Transport Triggered Architecture (TTA) type, for which a complete codesign toolset exists. The ex-isting tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the toolchain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. The decoder is realized into 21 processors that de-code QCIF resolution video at 20 frames per second with a 50MHz FPGA clock frequency. Index Terms — data flow computing, design automation, multiprocessor interconnection 1