Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture?

Abstract. The rapid growth of multimedia applications has been putting high pressure on the processing capability of modern processors, which leads to more and more modern multimedia processors employing paral-lel single instruction multiple data (SIMD) units to achieve high perfor-mance. In embedded system on chips (SOCs), shared memory multiple-SIMD architecture becomes popular because of its less power consump-tion and smaller chip size. In order to match the properties of some mul-timedia applications, there are interconnections among multiple SIMD units. In this paper, we present a novel program transformation technique to exploit parallel and pipelined computing power of modern shared-memory multiple-SIMD architecture. This optimizing technique can greatly reduce the conflict of shared data bus and improve the performance of applications with inherent data pipeline characteristics. Experimental re-sults show that our method provides impressive speedup. For a shared memory multiple-SIMD architecture with 8 SIMD units, this method obtains more than 3.6X speedup for the multimedia programs.