FIR Filter Implementation by Systolization using DA-based Decomposition

Abstract In this paper we present 1D and 2D systolic Distributed Arithmetic (DA) based structures that are designed for the implementation of Finite Impulse Response (FIR) filters. The paper compares the 1D DA based systolic structure with 1D systolic DA based decomposition method. The filters are implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using HDL and system metrics like Area, Gate Count, Maximum Usable Frequency and Power consumption are estimated for different filter orders and address lengths. The 1D systolic decomposition structure is also compared with the existing system generator implementation of DA FIR.. Results for an exemplary implementation are presented