Copper Electrodeposition for 3D Integration

Abstract-Two dimensional (2D) integration has been the tra-ditional approach for IC integration. Increasing demands for providing electronic devices with superior performance and functionality in more efficient and compact packages has driven the semiconductor industry to develop more advanced packaging technologies. Three-dimensional (3D) approaches address both miniaturi-zation and integration required for advanced and portable elec-tronic products. Vertical integration proved to be essential in achieving a greater integration flexibility of disparate technolo-gies, resulting in a general trend of transition from 2D to 3D in-tegration in the industry. 3D chip integration using through silicon via (TSV) copper is considered one of the most advanced technologies among all different types of 3D packaging technologies. Copper electrodeposition is one of technologies that enable the formation of TSV structures. Because of its well-known ap-plication for copper damascene interconnects, it was believed that its transfer to filling TSV vias would be easily adopted. However, as any new technology at its beginning, there are sev-eral challenges that need to be addressed and resolved before becoming a fully mature technology. This paper will address the TSV fill processes using copper electrodeposition, the advantages as well as difficulties associ-ated with this technology and approaches taken to overcome them. The effect of wafer design on process, including necessary process optimization that is required for achieving void-free filling will be discussed