EFFICIENT SERIAL AND PARALLEL IMPLEMENTATION OF PROGRAMMABLE FIR FILTERS BASED ON THE MERGING TECHNIQUE

This paper presents a novel architecture for the efficient implementation of parallel and serial programmable FIR filters. In the parallel merged architecture, both the input data and the coefficients operate in bit-parallel form. In the serial merged architecture, input data enters the circuit in Modified-Booth encoded digits, while the coefficients are kept in bit-parallel form. The proposed schemes are based on a low latency filter structure, where adjacent multiply-add units are merged to reduce the number of carry-save registers of the accumulation path to the half. The computa-tion of intermediate terms is implemented using the carry-save arithmetic. Based on theoretical estimation models of hardware complexity and switching activity, it is shown that the presented schemes result in circuits with reduced area and power consumption, compared to other parallel and serial FIR filter architectures presented in the bibliography. 1