Hewlett-Packard Company 1994

As described in the accompanying article, we are attempting to guard against a number of statistical tolerancing mechanisms, such as skew and jitter, that reduce the precision with which a clock signal can be delivered. Here we present an overview of these mechanisms.1 For the purpose of considering system timing issues, it is useful to separate the system state architecture into a timing environ-ment and a computation environment (see Fig. 1). The boundary between these two parts of the system is composed of the system state devices. Except for seg-ment delay times and communications locality, we don’t address the details of the computation environment here. The timing environment can be further broken down into three sections: the clock or phase generator, the clock distribution network, and the memory elements. The clock generator supplies the signal whose edges eventually dictate when switching occurs throughout the system. The clock generator determines the period, pulse width, number of phases, and relative phase separation of the clock waveform. The primary attributes of the generator to be specified at design tim