POWER- AND AREA-EFFICIENT SINGLE SISO ARCHITECTURE OF TURBO DECODER

In this paper, we propose a power- and area-efficient architecture of Turbo decoder. In order to improve the non-functional performance metrics such as power consumption and area, we use the trade-off method between bit error rate (BER) performance and the two non-functional performance metrics. Our proposed architecture shows about 16.7% reduction in power consumption and about 22.5 % reduction in area compared to the general architecture. Index Terms — trade-off method, data dependency, parallelism, sub-optimal initialization, single SISO architectur