An Enhanced Congestion-Driven Floorplanner

Abstract:- In this paper, a rectilinear-based congestion-driven floorplanning algorithm is presented to enhance the wire congestion and the CPU runtime. The proposed algorithm contains two stages, including the simulated-annealing (SA) based approach with the concept of ant algorithm (SANTA) and the nonlinear programming based method. The objective of the first stage and the second stage are to minimize the multiple objectives, such as the area, wire length and wire congestion, and to further improve the wire congestion of the local congested region without the area overhead, respectively. First, the effective concept of the ant algorithm is integrated into the multiple objectives floorplanner, which simultaneously minimizes area, wire congestion and the total wire length, to speedup the runtime. Besides, the nonlinear programming (NLP) based formulations are provided to perform the module reshaping, which maximizes the common length between two adjacent congested modules. For the floorplanner, the sequential-pair (SP) presentation is utilized to deal with the floorplan data at every iteration. For each iteration of the floorplanner, we first use SANTA to improve the neighbor searching and reduce the runtime. After performing the first state, we will obtain a floorplan with the objectives of the area, wire congestion and total length. For the intermediate floorplan, we select the two adjacent soft modules located at the most congested regions and divide the two soft modules into a set of connected sub-rectangles. Hence, we further reduce the congestion by enlarging the common boundary betwee