VLSI DESIGN AND IMPLEMENTATION OF 2-D INVERSE DISCRETE WAVELET TRANSFORM

This paper proposes a JPEG-2000 compliant architecture capable of computing the 2-D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex 2 FPGA