Improving Kernel Scalability by Lock-Aware Thread Migration

Multi-core architecture has been adopted by the chip manufacturers. Computers with two or four cores are com-mon. Trends seen from Intel’s 80-core [1] processor suggest that cores in a single chip are still increasing. Within ten years, each chip will embrace thousands of cores. Commodity operating systems, however, cannot scale well with the number of cores because the lock protect-ing the shared data structure in the kernel tends to be time-consuming when the lock contenders increase. This phe-nomenon can be observed easily on the future many cores even if only several instructions exist in the critical section. In the past, operating system developers exploit finer grain locks to remove this bottleneck and this method has been proven to be successful. However, as the cores increase ex-ponentially, making the critical section finer tends to be har