Design and Implementation of an FFT Processor with Efficient Memory Management

I In this thesis, we investigate several FFT implementations with the basic radix-2 algorithm, based on a single process element structure, conforming to the requirements of an OFDM system, such as DAB system, namely 12.288MHz or 24.576 MHz. In-place mode memory structure is used to minimize the hardware area. To increase the speed in data access between the butterfly-unit and the memory, memory partition is utilized. Also, pipelining is used in the butterfly-unit circuit to increase the throughput which in turn increases the overall speed. The result of this study may be used as basis for future research. To implement this FFT processor, VHDL is used to describe the circuit design and Xilinx ISE6.3 is used for synthesis. The simulation is performed using ModelSim 6.0 t