A low area and low power programmable baseband processor architecture

A fully programmable radio baseband processor archi-tecture is presented. The architecture is based on a DSP processor core and a number exible accelerators, con-nected via a congurable network. Design choices are mo-tivated by the inherent properties of the baseband algo-rithms used in different types of radio systems. A large de-gree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost al-lows very area and power efcient implementation of multi-standard radio baseband processors. A demonstrator chip for 802.11a/b/g physical layer baseband processing was manufactured in 0.18 m CMOS. The silicon area is 2.9 mm2, including all memories.