A TimeMultiplexed FPGA

steve.trimberger @ xilinx.com This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configura-tion of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 3011s. Inactive memory is acces-sible as block RAM for applications. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware. Background This paper reports on architecture development project that began in 1991. The architecture builds on the work of Ong [1995], who proposed rapidly reconfiguring an FPGA to increase logic capacity. Bhat [ 19931, DeHon [ 19951 and Tau [ 19951 also described rapidly-reconfigured FPGAs. These devices were deficient in at least one of the following critical areas: Device Capacity. Fundamentally, logic is shared to increase capacity. A base FPGA of low capacity is imprac-tical, since a larger non-time-multiplexed FPGA is faster and easier to use. State Storage. Although combinational logic can be shared, state values cannot. They must be stored or forwarded until they are used. Simplistic solutions to this problem result in FPGA logic resources consumed with saving state. Very little remains for implementing logic. Memory. Time-multiplexed systems consume memory for configuration data and for staged design data. Facilities must be provided for this data. 0 Static Logic. All systems include some logic that must always be active and cannot be multiplexed. A usable time-multiplexed device must be able to also supply this non-time-multiplexed logic. This paper is divided into three sections. First is an introduc-tion to the method of time multiplexing used in this architec-ture. The second section discusses modes of operation of a time-multiplexed device. The third section describes the device itself and highlights the device features and how they support the modes of operation