Assertion checker synthesis for FPGA emulation

Abstract — In the paper, we propose a method to synthesize SystemVerilog Assertion checkers for FPGA emulation. The main idea is to synthesize assertions based on finite input memory automata (FIMA) and use embedded RAM modules to con-struct shift register chain for storing the history of variables. The method does not consume logic ele-ments for storing the value and the shift register using the embedded RAM is much more efficient compared with the one uses the registers in logic elements. We also compare the proposed FIMA method with MBAC [1] method and a tool of FoCs [2]. I