, Surendra Kumar Tadi

Abstract — A Modern complex SOC has a number of different asynchronous clock domains and data is frequently transferred from one clock domain to another which needs to be synchronized. Designer uses many types of synchronizer, most commonly used synchronizer is 2 flop synchronizer which is mainly used for control signals, there are other types of synchronizer such as MUX synchronizer, FIFO synchronizer, these are used when a multi bit signal or a bus needs to be synchronized in destination domain. Due to large design size and presence of multiple asynchronous clocks in a SOC, synchronizer is needed at thousands of places and it becomes very important to ensure if proper synchronization is done at all required places. STA does not cover clock domain crossing paths while gate level simulation’s are very limited since it does not cover all the CDC paths, it flags violation on CDC path only if timing’s are not met. As a standard practice, CDC verification for a SOC is mostly done using formal tools such as ―lec –verify‖, Questa CDC solution etc. These tools perform structural CDC checks for a given design. This paper explains about clock domain crossing requirement, synchronizer structure and a methodology to find out various issues in structural CDC checks. It also explains about reset synchronizer requirement & its verification. Keywords-- CDC, Clock domain crossing verification, Synchronizers,Gate level simulation. I