Submitted in part fulfilment for the degree of MEng. Investigating Serial Microprocessors for FPGAs

Number of words = 19,035, as counted by detex | wc-w. This includes the body of the report, and Appendices A and B. Typical microprocessor architectures process data 32 or 64 bits at a time. A new ar-chitecture is proposed for FPGAs that processes data a single bit at a time, that could lead to a microprocessor with very little logic usage. Such a microprocessor is suitable for FPGAs due to the limited interconnect resources available. It is believed that an architecture that processes data in this way will occupy minimal resources, but will require a relatively large amount of clock cycles to process data. It is hoped that it will be possible to synthesise the resulting microprocessor with such low logic utilisation that it will be able to operate at a high clock frequency that will partially offset the amount of clock cycles needed. Furthermore, it is hypothesised that when considering performance per unit of logic that the bit-serial processor will be able to outperform contemporary softcore designs. With the rise in popularity of multicore processors, this may ultimately lead to multiple bit-serial cores being used in favour of a singl