An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors

In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex scheduling logic results in the formation of a hot spot on the processor chip. Consequently, the latency and power consumption of the dynamic scheduler are two of the most crucial design issues when developing a high-performance microprocessor. We propose an instruction wakeup scheme that remedies the speed and power issues faced with conventional designs. This is achieved by a new design that separates RAM cells from the match circuits. This separated design is such that the advantages of the CAM and bit-map RAM schemes are retained, while their respective disadvantages are eliminated. Specifically, the proposed design retains the moderate area advantage of the CAM scheme and the low power and low latency advantages of the bit-map RAM scheme. The experimental results show that the proposed design saves power consumption by 80 % compared to the traditional CAM-based design and 18 % to the bit-map RAM design, respectively. In speed, the proposed design reduces an average of 77 % in the wakeup latency compared to the conventional CAM-based design and an average of 33 % reduction of the latency of the bit-map RAM design. For an 8-issue superscalar processor, the proposed design reduces the power consumption of the conventional wakeup logic by 80%, while simultaneously increasing the Instruction Count per nano-second (IPns) by a factor of approximately 2.5 times with a moderate area cost