Fixed priority scheduling for reducing overall energy on variable voltage processors

While Dynamic Voltage Scaling (DVS) is an efficient tech-nique in reducing the dynamic energy consumption of a CMOS processor, methods that employ DVS without con-sidering leakage current are quickly becoming less efficient when considering the processor’s overall energy consump-tion. A leakage conscious DVS voltage schedule may require the processor to run at a higher-than-necessary speed to ex-ecute a given set of real-time tasks, which can result in a large number of idle intervals. To effectively reduce the en-ergy consumption during these idle intervals, and therefore the overall energy consumption, the DVS schedule must ju-diciously allow the processor to enter and leave the power down state during these idle intervals, while considering the time and energy cost of doing so. In this paper, we present a scheduling technique that can effectively reduce the over-all energy consumption for hard real-time systems scheduled according to a fixed priority (FP) scheme. Experimental re-sults demonstrate that a processor using our strategy con-sumes as less as 15 % of the idle energy of a processor em-ploying the conventional strategy. 1