1 Shorten and Simplify SoC Verification using a Generic eVC

Abstract: This paper describes an e Verification Component (eVC) that has been used in the verification of four separate bus based SoCs with only minimal modification. The user simply describes the topology of the design and testbench to the eVC, and the eVC uses this information to instantiate the correct bus eVCs, to create the required scoreboards, to generate customised functional coverage, to control the default stimuli so that only realistic transactions are generated, and to perform full bus infrastructure verification. Individual testbenches can define a working topology to reduce the scope of the testbench, improve performance, and reduce third party license usage. The eVC greatly increases the user’s productivity b