1 A PC-Based ATM Link Delay Simulator

We have implemented a low-cost, flexible, and easy-to-use Link Delay Simulator (LDS) for OC-3 (155 Mbps) ATM links using a commodity Pentium PC equipped with a single PCI ATM host adapter. The LDS is a useful tool for studying the effects of varied link delays on protocol behavior. The LDS demands 100 % sustained, full-duplex bandwidth from the ATM host interface. This performance requirement is significantly greater than those of typical applications. The LDS cannot use the host interface in whole-packet (AAL5) mode, essential for attaining sustained high-performance on many host adapters. Our LDS implementation meets the bandwidth requirements of a full-duplex OC-3 link (300+ Mbps over the PCI bus) by aggressively using burst-mode DMA, large network buffers, device polling to reduce host CPU interrupts, and null cell buffering to obviate scheduling computations for preserving inter-cell spacing of the delayed data. The contributions of this work are a detailed description of the LDS architecture and implementation, and a discussion of host adapter architecture for high-performance, real-time, network applications. Other real-time systems also present streaming input, and require careful attention to buffer sizing, interrupt load on the host CPU, and bus performance; we offer a detailed study of the LDS as one such system. To show the utility of the LDS, we use it to validate others ’ analytic predictions of TCP fairness for competing flows in the presence of varying round-trip delay. 1