Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment

The sustained progress of VLSI technology has altered the land-scape of routing which is a major physical design stage. For tim-ing driven routings, traditional approaches which consider only wire self capacitance become inadequate since the wire delay is affected more by coupling capacitance in ultra-deep submicron de-signs. Furthermore, the technology scaling dramatically increases the likelihood of the antenna problem in manufacturing and re-quests corresponding considerations in the routing stage. In this paper, we propose techniques that can be applied to handle the cou-pling aware timing and the antenna problem simultaneously during layer assignment which is an important step between global rout-ing and detailed routing. An improved probabilistic coupling ca-pacitance model is suggested for coupling aware timing optimiza-tion without performing track assignment. The antenna avoidance problem is modeled as a tree partitioning problem with a linear time optimal algorithm solution. This algorithm is customized to guide antenna avoidance in layer assignment. A linear time optimal jumper insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of 270ps timing slack improvement validated by track assignment, 76 % antenna violation reduction and 99 % via viola-tion reduction