Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipments (ATEs) makes it hard to test the circuit while in the field. In this report, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The seeds are encoded in hardware. The seeds we use are deterministic so 100 % fault coverage can be achieved. Our technique causes no performance overhead and does not change the original circuit under test. Also, the technique we present is applicable for single-stuck-at faults as well as transition faults. Built-in reseeding is based on expanding ever...
The move to deep-sub-micron processing technology and the increasing complexity of a single chip mak...
A new low power LP scan based built in self test BIST technique is proposed based on weighted pseudo...
The move to deep-sub-micron processing technology and the increasing complexity of a single chip mak...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
In this paper we present a novel reseeding technique for accumulator-based Test Pattern Generation s...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented o...
Reseeding is used to improve fault coverage of pseudo-random testing. The seed corresponds to the in...
[[abstract]]Generally, there exist random-pattern resistant faults that result in the poor fault cov...
Generally, there exist random-pattern resistant faults that result in the poor fault coverage in Bui...
A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over ...
In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-polynomial Linear ...
Experience has shown that an excessive time penalty can be incurred when testing large scan circuits...
Test cost comprises a substantial portion of producing an integrated circuit. As a result, structura...
The move to deep-sub-micron processing technology and the increasing complexity of a single chip mak...
A new low power LP scan based built in self test BIST technique is proposed based on weighted pseudo...
The move to deep-sub-micron processing technology and the increasing complexity of a single chip mak...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
In this paper we present a novel reseeding technique for accumulator-based Test Pattern Generation s...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented o...
Reseeding is used to improve fault coverage of pseudo-random testing. The seed corresponds to the in...
[[abstract]]Generally, there exist random-pattern resistant faults that result in the poor fault cov...
Generally, there exist random-pattern resistant faults that result in the poor fault coverage in Bui...
A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over ...
In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-polynomial Linear ...
Experience has shown that an excessive time penalty can be incurred when testing large scan circuits...
Test cost comprises a substantial portion of producing an integrated circuit. As a result, structura...
The move to deep-sub-micron processing technology and the increasing complexity of a single chip mak...
A new low power LP scan based built in self test BIST technique is proposed based on weighted pseudo...
The move to deep-sub-micron processing technology and the increasing complexity of a single chip mak...