Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors

Scalable distributed shared-memory architectures rely on coher-ence controllers on each processing node to synthesize cache-coherent shared memory across the entire machine. The coher-ence controllers execute coherence protocol handlers that may be hardwired in custom hardware or programmed in a protocol proces-sor within each coherence controller. Although custom hardware runs faster, a protocol processor allows the coherence protocol to be tailored to specific application needs and may shorten hardware development time. Previous research show that the increase in ap-plication execution time due to protocol processors over custom hardware is minimal. With the advent of SMP nodes and faster processors and net-works, the tradeoff between custom hardware and protocol proces-sors needs to be reexamined. This paper studies the performanc