TEMS]: Real-time and embedded systems

Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avion-ics. Specifications written in Esterel are based on the underlying “synchrony hypothesis”, where the computation/communication as-sociated with the processing of all events occurring within the same “clock tick ” are assumed to happen instantaneously (or in zero time). In reality, Esterel specifications get compiled to implemen-tations (such as C code) which do not satisfy the perfect synchrony assumption. Hence, platform-specific timing analysis of such im-plementations is an important research topic. Interest in this area has lately been renewed with the recent advances in Worst-case Ex-ecution Time (WCET) analysis techniques. In this paper we per-form WCET analysis on sequential C code and exploit the struc-ture of the code generated from Esterel specifications to obtain tight WCET estimates. Such estimates can validate Esterel-level assumptions on the instantaneous processing of signals or events that occur together. More importantly, they can be used to identify parts of the specification which might pose as timing/performance bottlenecks with respect to the underlying platform. This is done by exploiting traceability links between Esterel specifications and the generated C code, which map the time-critical computations at the C-level back to the Esterel-level. This not only allows a designer to optimize or simplify Esterel specifications, but also choose/configure suitable implementation platforms. We show the results of our WCET analysis on a set of standard Esterel bench-marks and illustrate the utility of our model-code traceability tech-nique using an Esterel specification of a reflex game application