Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs

This paper proposes a novel cache architecture suit-able for merged DRAM/logic LSIs, which is called “dynamically variable line-size cache (D-VLS cache)”. The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to im-prove the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement achieved by a direct-mapped D-VLS cache is about 27%, compared to a con-ventional direct-mapped cache with fixed 32-byte lines.