Static timing: Back to our roots

Abstract — Existing static timing methodologies apply various techniques to address increasingly larger process variations. The techniques include multi-corner timing, on-chip variation (OCV) derating coefficients, and path-based common path pessimism re-moval (CPPR) procedures. These techniques, however, destroy the benefits of linear run-time and incrementality possessed by classi-cal static timing. The major contribution of this work is an effi-cient statistical timing methodology with comprehensive modeling of process variations, while at the same time retaining those key benefits. Our methodology is compatible with existing character-ization methods and scales well to large chip designs. To achieve this goal, three techniques are developed: (1) building the statistical delay model based on existing multi-corner library characteriza-tion; (2) modeling spatial correlation in a scalable manner; and (3) avoiding the time-consuming CPPR procedure by removing com-mon path pessimism in the clock network by an incremental block-based technique. Experimental results on industrial 90 nm ASIC designs show that the proposed timing methodology correctly han-dles all types of process variation, achieves high correlation with traditional multi-corner timing with more than 4 × speedup, and is a vehicle for pessimism reduction. I