A Data Protection Unit for NoC-based Architectures

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the com-munication infrastructure of next-generation embedded de-vices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network In-terface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of proces-sors requesting access to data locations in a shared memory- in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore dif-ferent alternative implementations and demonstrate how the DPU unit does not affect the network latency if the mem-ory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC imple-mentations of the Data Protection Unit