Lifetime Prediction Model for Anaio Based on Drain Conductance Degradation due to

MOSFET degradation due to hot carrier injection is the most important reliability issue in realizing submicron ultra-large scaled integrated circuits. This degradation has been widely studied and lifetime simulators have also been developed for digital circuit operation [1]-[2]. On the other hand, the degradation of analog device parameters such as drain conductance due to hot carrier injection are not clearly understood and modeled. In this paper, we propose, for the first time, a physical model of analog drain conductance, gd degradation based on mobility reduction due to hot carrier generated interface states and show a reliability design guideline for analog devices. Fig. 1 shows gain degradation of a single MOSFET amplifier with a constant current source (Fig. 2) as a function of DC stress time. Since the gain of the amplifier is given by gain=g,/&, gm and were also measured and dg,=lg,-g,l and dgd=lgd0-gdl were plotted in Fig. 1. It has been found that the main cause of the gain degradation was gd degradation rather than &n degradation. Our model of gd degradation is based on the gradual channel approximation (GCA) and mobility reduction due to interface states generated by hot carrier injection [3]. When distribution of interface states generated by hot carrier injection is assumed to be a step function over the damaged region, the generated interface state density, Nits, is given by [4] where Le8 is the effective gate length, L h g the length of the damaged region and a the mobility reduction factor. In the saturation region, a depletion region is formed between the pinch-off point and the drain as shown in Fig. 3. The drain current equation in the saturation region is given b