Add to ORKGAbstract — This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization dis-regard clock tree variation, we consider both. Using both clock and data-path variations together, we present a novel sensitivity-matching algorithm that allows clock tree skews to be intention-ally correlated with data-path sensitivities to ameliorate timing violations due to variation. Our statistical tuning shows an im-provement in terms of expected clock skew and clock skew varia-tion over previously published robust algorithms. I
In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer ...
The design of clock distribution networks in synchronous digital systems presents enormous challenge...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
Clock distribution is vital to all synchronous integrated circuits; a poor clock distribution networ...
Abstract — This work develops an analytic framework for clock tree analysis considering process vari...
In synchronous circuit design, data is processed in an orderly fashion with the help of sequential e...
This work tackles a problem of clock power minimization within a skew constraint under supply voltag...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer ...
In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in d...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...
In this paper, we investigate the effect of multilevel networks on clock skew. We first define the s...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer ...
The design of clock distribution networks in synchronous digital systems presents enormous challenge...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
Clock distribution is vital to all synchronous integrated circuits; a poor clock distribution networ...
Abstract — This work develops an analytic framework for clock tree analysis considering process vari...
In synchronous circuit design, data is processed in an orderly fashion with the help of sequential e...
This work tackles a problem of clock power minimization within a skew constraint under supply voltag...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer ...
In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in d...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...
In this paper, we investigate the effect of multilevel networks on clock skew. We first define the s...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer ...
The design of clock distribution networks in synchronous digital systems presents enormous challenge...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...