Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power

Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be real-ized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual struc-tures and their control. A common theme to these studies is exploration of the configuration space and use of sys-tem IPC as feedback to guide reconfiguration. However, when multiple structures adapt in concert, the number of possible configurations increases dramatically, and assign-ing causal effects to IPC change becomes problematic. To overcome this issue, we introduce designs that are reconfig-ured solely on local behavior. We introduce a novel cache design that permits direct calculation of efficient configura-tions. For buffer and queue structures, limited histogram-ming permits precise resizing control. When applying these techniques we show energy savings of up to 70 % on the in-dividual structures, and savings averaging 30 % overall for the portion of energy attributed to these structures with an average of 2.1 % performance degradation.