Online Protocol Testing for FPGA Based Fault Tolerant Systems

In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed- in the paper the lowest level is pre-sented. The definition of dedicated language for the de-scription of possible communication faults is presented. The core generator is used to produce VHDL code describing the behaviour of the checker. 1. Instructions Fault-tolerance is an important system metric for many operating environments, from automotive to space explo-ration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing