A low-power parallel design of discrete wavelet transform using subthreshold voltage technology

The Discrete Wavelet Transform (DWT) is a means to ana-lyze the frequency content of a signal and has extensive uses, including the JPEG2000 codec. Many portable and battery operated applications of DWT are expected in the near fu-ture that require a low power implementation of this trans-form. In this paper, a parallel VLSI implementation of a 2D lifting-based DWT processor is presented that is scalable from 2 to 256 parallel units. This design benefits from an efficient data distribution module to the parallel units, which constitutes a small overhead, and is able to significantly ben-efit from voltage scaling to achieve energy efficiency. In our design, the number of parallel units is increased and their speed is reduced through voltage scaling, while maintaining a constant throughput. Our results show that the optimal op-erating voltage of the parallel units, for a target throughput of 200MHz, is 386mV. This is below the threshold voltage, which is the voltage that turns the transistors on. Since oper-ating a circuit in subthreshold voltage consumes 100+ times less power than running it at nominal voltage, our design is able to provide the same throughput as a reference pipelined implementation with 26 times less power consumption