Within-die Process Variations: How Accurately Can They Be Statistically Modeled?

Abstract — Within-die process variations arise during inte-grated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the perfor-mance of ICs from their designers ’ original intent. These devi-ations reduce the parametric yield and revenues from integrated circuit fabrication. In this paper we provide a complete treatment to the subject of within-die variations. We propose a scan-chain based system, vMeter, to extract within-die variations in an au-tomated fashion. We implement our system in a sample of 90nm chips, and collect the within-die variations data. Then we propose a number of novel statistical analysis techniques that accurately model the within-die variation trends and capture the spatial cor-relations. We propose the use of maximum-likelihood techniques to find the required parameters to fit the model to the data. The accuracy of our models is statistically verified through residual analysis and variograms. Using our successful modeling tech-nique, we propose a procedure to generate synthetic within-die variation patterns that mimic, or imitate, real silicon data. I