Berkeley,

In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern proces-sors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees. We describe an alternative in this paper: a SPARC-based pro-cessor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, inde-pendent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) archi-tecture through example applications running in simulation