A Memory Aware Behavioral Synthesis Tool for Real-Time VLSI Circuits

We introduce a new approach to take into account the mem-ory architecture and the memory mapping in the Behav-ioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the syn-thesis, and defined a Memory Constraint Graph and an ac-cessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory con-straints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral syn-thesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area