Total Power Optimization Combining Placement, Sizing and

Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power and timing are often conflicting objectives during optimization. In this paper, we propose a novel total power optimization flow under performance constraint. Instead of using placement, gate sizing, and multiple-Vt assignment techniques independently, we combine them together through the concept of slack distribution management to maximize the potential for power reduction. We propose to use the linear pro-gramming (LP) based placement and the geometric programming (GP) based gate sizing formulations to improve the slack distribu-tion, which helps to maximize the total power reduction during the Vt-assignment stage. Our formulations include important practi-cal design constraints, such as slew, noise and short circuit power, which were often ignored previously. We tested our algorithm on a set of industrial-strength manually optimized circuits from a multi-GHz 65nm microprocessor, and obtained very promising results. To our best knowledge, this is the first work that combines place-ment, gate sizing and Vt swapping systematically for total power (and in particular leakage) management. 1