Characterization of Logic Circuit Techniques for High Leakage CMOS Technologies

Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, tech-niques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this pa-per, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hy-pothetical technology. The framework also allows exploration of optimal mixing of techniques. Categories and Subject Descriptors