Evaluation of low-leakage design techniques for field-programmable gate arrays

In this paper we evaluate the trade-os between various low-leakage design techniques for eld programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplex-ers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multi-plexers and routing switches are proposed and their design trade-os are presented based on transistor-level simulation, physical design, and impact on overall system performance. We nd that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques be-ing evaluated in our study, the impact on chip area is very minimal to an increase of 15 % − 30%