IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL t) NO 2. FEBRUARY 1990 203 Design for Test Using Partial Parallel Scan

Abstract-Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the draw-back that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. We present a new scan design tech-nique termed partial parallel scan which reduces test application effort by 1 to 2 orders of magnitude. Theoretical and practical aspects of the new design method are discussed. The practical use of the partial par-allel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools. Index Terms-Testable design, testing and maintenance, CAD for fault-tolerance, NP-complete, scan design, partial scan. I