A New Efficient Normalization VLSI Architecture for MAP Decoder

This paper presents a new efficient normalization VLSI architecture for MAP decoder which can provides the high speed decoding. In our design, we propose a novel normalization method, called low latency normalization, which can speed up the decoder throughput about 18%~34 % and can reduce area of state metric memory (SMM) about 13 % in comparison with other SISO decoders. For demonstrating the architecture of the low latency normalization, we have designed a MAP decoder with TSMC CMOS 0.35µm 2P4M technology. The chip occupies 2.3µm*2.3 mm2, consumes 90mW and supports a 43Mbps data rate. Turbo code was introduced in 1993[1] and has becom