A Compiler-in-the-Loop Framework to Explore Horizontally Partitioned Cache Architectures

Horizontally Partitioned Caches (HPCs) are a promising ar-chitectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using HPC architectures is very sensitive to the HPC parame-ters. Therefore it is very important to explore the HPC design space and carefully choose the HPC parameters that result in minimum energy consumption for the application. However, since in HPC architectures, the compiler has a significant im-pact on the energy consumption of the memory subsystem, it is extremely important to include compiler while deciding the HPC design parameters. While there has been no previous approaches to HPC design exploration, existing cache design space exploration methodologies do not include the compiler effects during DSE. In this paper, we present a Compiler-in-the-Loop (CIL) Design Space Exploration (DSE) methodology to explore and decide the HPC design parameters. Our experi-mental results on HP iPAQ h4300-like memory subsystem run-ning benchmarks from the MiBench suite demonstrate that CIL DSE can discover HPC configurations with up to 80 % lesser energy consumption than the HPC configuration in the iPAQ. In contrast, tradition simulation-only exploration can discover HPC design parameters that result in only 57 % memory sub-system energy reduction. Finally our hybrid CIL DSE heuris-tic saves 67 % of the exploration time as compared to the ex-haustive exploration, while providing maximum possible en-ergy savings on our set of benchmarks. I