Leakage power reduction using bitwidth optimization

Leakage power dissipation constitutes an increasing frac-tion of the total power in modern semiconductor tech-nologies. Designing power efficient products will require consideration of leakage power in the earliest phases of de-sign. This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power de-sign. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized re-sulting in significant leakage power reduction besides dy-namic power reduction. In our experiments for several real embedded applications, power reduction without per-formance penalty are reported range from about 21.5 % to 66.2 % of leakage power, and 14.5 % to 59.2 % of dynamic power